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Job Information
Job title

DRAM Design Engineer

Company Qimonda
Wage between $0.00 - $0.00 Annually
Location United States, Vermont, Williston
Employment type Full Time
Education Not Specified
Year Experience 4 - 5 Years of Practical Experience
Travel None
Published on 9/10/2007
Description
Qimonda NA, the new memory company carved out of Infineon Technologies NA on May 1, 2006, is a Top 4 DRAM company worldwide (according to Gartner Dataquest, February 2006), a leader in 300mm manufacturing, and one of the top suppliers of DRAM products for the PC and Server markets. Qimonda, currently a wholly-owned subsidiary of Infineon, is headquartered in Munich and has generated net sales of 2.8 billion EUR in last fiscal year 2005. We have approximately 12,000 employees worldwide including 1,700 in R&D with access to five 300mm manufacturing sites on three continents. And we operate five major R&D facilities, including our lead R&D-center in Dresden. With a historical emphasis on PC and server products, the company is now focusing on products for graphics, mobile and consumer applications using its power-saving trench technology.

Qimonda AG is searching for an experienced DRAM Design Engineer to work in our Williston, Vermont facility. Positions are open for experienced DRAM Design Engineers familiar with high level description languages for synthesized blocks and chip modelling (HDL, Verilog) as well as full custom circuit knowhow. The Design Engineer will be responsible for a part of a DRAM design within a team of 5-10 design engineers, working closely with the design team leader and with layout engineers assigned to the specific project.



DESCRIPTION:
The DRAM Design Engineer's main functions are but not limited to:

Support design teams with Verilog and Full Custom simulation know-how
Develop full custom and synthesized logic circuitry with reduced operating current for critical low power DRAM blocks, enhance the verification environment and methodology during full chip simulation with state of the art simulation techniques
Contribute to block migration from formerly full custom designed blocks to synthesized implementations where possible


REQUIREMENTS:
In accomplishing this task, the engineer must have the following skills:

Bachelor's or Master's degree in Electrical Engineering or Physics is required
At least 3 years of experience in transistor level circuit design, behavioral modeling and state of the art design and verification tools (e.g. Cadence Composer, HSPICE and Timemill)
Experience with DRAM, SRAM and/or Pseudo-SRAM design and CMOS IC design methodologies is required, experience with Verilog and Perl programming is a plus


QUALIFICATIONS:

Engineer 1: MSEE or BSEE with no industry experience
Engineer 2: MS + 1 year experience or BS + 6 years experience
Senior Engineer: MS + 2 years experience or BS + 7 years experience
Staff Engineer: MS + 5 years experience or BS + 10 years experience
Senior Staff Engineer: MS + 7 years experience or BS + 12 years experience
Principal: MS + 10 years experience or BS + 15 years experiencedf-tc

Experience/Skills
See above

Other desired skills:
DRAM Design Engineer
This job has expired.